Sessions
Test Coverage Report for CIVL 1.13 r4606 Regression Suite
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edu.udel.cis.vsl.civl.transform.IF
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ShortCircuitTransformer
ShortCircuitTransformer
Element
Missed Instructions
Cov.
Missed Branches
Cov.
Missed
Cxty
Missed
Lines
Missed
Methods
Total
0 of 17
100%
0 of 0
n/a
0
2
0
4
0
2
transform(AST)
100%
n/a
0
1
0
2
0
1
ShortCircuitTransformer(ASTFactory)
100%
n/a
0
1
0
2
0
1