Dynamic Barrier Relaxations for Explicit Stencil Computations

Next generation HPC computing platforms are likely to be characterized by significant, unpredictable non-uniformities in execution time among compute nodes and cores. These inherent load imbalances are expected to arise from a variety of sources---manufacturing discrepancies, dynamic power management, runtime component failure, OS jitter, software mediated resiliency, and TLB/- cache performance variations, etc. It is well understood that existing algorithms with frequent points of bulk synchronization will perform relatively poorly in the presence of these performance fluctuations. Thus, re-casting classic bulk-synchronous algorithms into more asynchronous, course grained parallelism is a critical area of research for next generation computing. In the present analysis we propose a robust class of parallel algorithms for explicit stencil computations in the presence of such non-uniformities in process execution time. These algorithms are benchmarked using the 2D heat equation as a model problem, and they are tested in the presence of simulated nonuniform computational noise. The performance is compared to a classic bulk synchronous implementation of the model problem.

@TechReport{hammouda-siegel-siegel:2013:dynamic-tr,
	author = {Adam Hammouda and Andrew R. Siegel and Stephen F. Siegel},
	title = {Dynamic Barrier Relaxations for Explicit Stencil Computations},
	institution = {Department of Computer and Information Sciences,
	University of Delaware},
	year = {2013},
	number = {UDEL-CIS-2013/002}
}