| processUnaryNode(OperatorNode) |  | 0% | | 0% | 14 | 14 | 54 | 54 | 1 | 1 |
| postIncrementReplacement(ExpressionNode) | | 0% | | n/a | 1 | 1 | 31 | 31 | 1 | 1 |
| preIncrementReplacement(ExpressionNode) | | 0% | | n/a | 1 | 1 | 27 | 27 | 1 | 1 |
| postDecrementReplacement(ExpressionNode) | | 0% | | n/a | 1 | 1 | 26 | 26 | 1 | 1 |
| signedToUnsigned(ExpressionNode) | | 0% | | 0% | 7 | 7 | 27 | 27 | 1 | 1 |
| preDecrementReplacement(ExpressionNode) | | 0% | | n/a | 1 | 1 | 20 | 20 | 1 | 1 |
| processUnsignedArithNode(OperatorNode) |  | 36% | | 20% | 6 | 7 | 22 | 34 | 0 | 1 |
| getBound() | | 0% | | 0% | 2 | 2 | 10 | 10 | 1 | 1 |
| transformCore(AST) | | 89% | | 45% | 11 | 12 | 3 | 26 | 0 | 1 |
| processIntDivNode(OperatorNode) | | 90% | | 57% | 6 | 8 | 3 | 31 | 0 | 1 |
| processIntegerOperation(ASTNode) | | 93% | | 68% | 7 | 12 | 1 | 13 | 0 | 1 |
| processOtherNodes(ASTNode) | | 96% | | 93% | 2 | 16 | 1 | 23 | 0 | 1 |
| linkUnsignedArithLibrary(SequenceNode) | | 100% | | 75% | 6 | 13 | 0 | 19 | 0 | 1 |
| linkIntDivLibrary(SequenceNode) | | 100% | | 77% | 4 | 10 | 0 | 17 | 0 | 1 |
| IntOperationWorker(ASTFactory, Map, CIVLConfiguration) | | 100% | | n/a | 0 | 1 | 0 | 8 | 0 | 1 |