edu.udel.cis.vsl.civl.model.common.statement

Element	Missed Instructions	Cov.	Missed Branches	Cov.	Missed	Cxty	Missed	Lines	Missed	Methods	Missed	Classes
Total	2,535 of 4,045	37%	210 of 328	36%	256	401	476	869	134	237	6	25
CommonMPIIrecvStatement		0%		0%	18	18	37	37	12	12	1	1
CommonMPIRecvStatement		0%		0%	18	18	37	37	12	12	1	1
CommonMPIIsendStatement		0%		0%	18	18	37	37	12	12	1	1
CommonMPISendStatement		0%		0%	17	17	36	36	11	11	1	1
StatementList		9%		0%	34	37	58	65	22	25	0	1
StatementSet		15%		7%	31	36	58	68	18	22	0	1
CommonMPIWaitStatement		0%		0%	13	13	32	32	7	7	1	1
CommonAssertStatement		60%		48%	21	38	42	95	5	14	0	1
CommonMallocStatement		48%		36%	16	29	22	63	3	15	0	1
CommonMPIBarrierStatement		0%		0%	9	9	21	21	6	6	1	1
CommonReturnStatement		50%		45%	10	20	21	43	3	9	0	1
CommonCallStatement		80%		71%	15	42	17	102	3	16	0	1
CommonWaitStatement		38%		0%	6	12	18	31	3	9	0	1
CommonAssumeStatement		60%		33%	6	12	11	32	3	9	0	1
CommonAtomicLockAssignStatement		26%		0%	2	3	4	7	1	2	0	1
CommonAssignStatement		86%		86%	6	24	7	46	3	13	0	1
CommonNoopStatement		34%		0%	3	6	7	13	2	5	0	1
CommonChooseStatement		36%		n/a	2	3	2	5	2	3	0	1
CommonSwitchBranchStatement		58%		0%	2	4	3	11	1	3	0	1
CommonGotoBranchStatement		52%		n/a	1	2	1	5	1	2	0	1
CommonNoopStatement.NoopKind		88%		n/a	2	4	0	2	2	4	0	1
CommonStatement		96%		79%	4	27	2	60	1	20	0	1
CommonAtomBranchStatement		61%		0%	2	3	3	7	1	2	0	1
CommonLoopBranchStatement		100%		100%	0	3	0	7	0	2	0	1
CommonIfElseBranchStatement		100%		100%	0	3	0	7	0	2	0	1