edu.udel.cis.vsl.civl.model.common.statement

ElementMissed InstructionsCov.Missed BranchesCov.MissedCxtyMissedLinesMissedMethodsMissedClasses
Total4,828 of 5,63814%342 of 41317%4235189051,1442333071828
CommonMPIRecvStatement7610%120%2525109109191911
CommonCallStatement48522532%503340%38648314872101
StatementList4650%370%49499595292911
CommonAssertStatement3798919%47713%36447810891701
CommonMallocStatement3053811%340%31356881141801
CommonStatement29211027%22724%2137488872101
CommonMPIIrecvStatement2850%120%22224141161611
CommonMPIIsendStatement2810%120%22224141161611
CommonMPISendStatement2680%120%22224141161611
StatementSet2250%280%40407272262611
CommonMPIWaitStatement1850%120%17173636111111
CommonReturnStatement1535225%21519%1725305041201
CommonWaitStatement1210%60%15153434121211
CommonMPIBarrierStatement1180%60%13132525101011
CommonAssignStatement11116259%131959%1432257051601
CommonAssumeStatement784034%60%715193341201
CommonAtomicLockAssignStatement460%20%6611115511
CommonSwitchBranchStatement380%20%4411113311
CommonStatement.new Object() {...}330%n/a11111111
CommonCallStatement.new Object() {...}330%n/a11111111
StatementList.new Object() {...}330%n/a11111111
CommonNoopStatement301432%20%5910164801
CommonChooseStatement300%n/a44664411
CommonGotoBranchStatement210%n/a22552211
CommonAtomBranchStatement180%20%33772211
CommonIfElseBranchStatement180%20%33772211
CommonNoopStatement.NoopKind96988%n/a24022401
CommonLoopBranchStatement71161%20%23371201